Itanium® Architecture for Programmers


Recent and future Itanium processors

Since the publication of our book, which was based on the Itanium processor code-named McKinley, Moore's law has permitted the evolution of additional implementations. We mention some of these here as well as hints about future products.

We do not aspire to predict the future, but we are as curious as anyone else about what may lie ahead. The material in the tables below comes either from vendor web sites or from other places on the Internet.

Road map information from Intel web sites and sources
2003-2006 2006 2007 2010 2012?
Code names

MP (high-end)

DP (low-end)






DP Montvale


Processor series     9000 9100 9300
Process 130 nm 90 nm 90 nm 65 nm
Die size 432 sq mm 596 sq mm 596 sq mm
Billions of transistors 0.592 1.720 1.720
L3 cache (max per core) 9 MiB 12 MiB 12 MiB 6 MiB
Physical memory addressing 50 bits 50 bits 50 bits 50 bits
Front-side bus speed (max) 667 MHz 533 MHz 667 MHz n/a
Processor speed (max) 1.66 GHz 1.60 GHz 1.66 GHz 1.73 GHz
Power (max per chip) 122 W 104 W 104 W 185 W
Pin-compatibility with Itanium 2     yes yes yes no
Core multiplicity (max) single dual dual quad
Speculation from other web sites or trade press
2010 2012 2014? later
Code name Tukwila

(formerly Tanglewood)

(technology from Alpha)

(on-chip memory controller)

Dimona (budget version)
Poulson Kittson
Pin-compatibility with series 9300     yes yes
Process 65 nm 32 nm
Die size 699 sq mm
Millions of transistors 2.046
L3 cache (max per core)
Processor speed(s) >1.7 GHz
Core multiplicity (max) 4 cores 6 to 10 cores   maybe 16


Other 64-bit processors

While this page is part of a web site in support of our book about Itanium architecture, we are interested in other architectures also. The following processors have been mentioned recently in articles in the trade press.


Advanced Micro Devices extended the industry-standard x86 CISC architecture from a 32-bit datapath with only 8 integer registers to the 64-bit AMD64 instruction set architecture with 16 integer registers. Beginning with Opteron processors intended for the server market and continuing with Athlon64 processors for desktop systems, this transition extended to the Turion and finally in 2006 to the Sempron processors for mobile systems.


Because of prior legal settlements, Intel has certain cross-licensing agreements in place with AMD. Intel's EM64T (Extended Memory 64 Technology), with instruction extensions essentially conforming to the AMD64 architecture, first reached the market as 64-bit Xeon processors in 2004. Subseqently, Intel renamed its several lines of 64-bit processors as implementations of Intel 64 architecture.

VIA Technologies

Beginning in 2008, Taiwan-based VIA added the Nano family of low-power processors with 64-bit capability. VIA processors are designed by Centaur Technology, a Texas-based wholly owned subsidiary.


IBM has based many of its server systems on its own POWER (Performance Optimization with Enhanced RISC) family of processors, which have had 64-bit capability since the POWER3 of 1998. POWER7 chips and associated lines of servers were introduced in 2010.

IBM, Apple, and Motorola (later spun off as Freescale) collaborated on PowerPC processors, which were derivatives of IBM's Power architecture and used in Apple Macintosh products until 2006. Motorola and Freescale produced only 32-bit PowerPC processors; IBM furnished some 32-bit processors as well as the 64-bit "G5" to Apple.

IBM codeveloped a Cell Broadband Engine processor with Toshiba and Sony for use in gaming stations and other multimedia appliances or servers; it has a 64-bit PowerPC processing core supplemented by eight special-purpose engines for handling graphics or numeric calculations.


Freescale Semiconductor, a spinoff from Motorola, produces QorIQ communications processors conforming to the Power architecture, now including 64-bit support.


Like the MIPS architecture (see below), the Sparc architecture began as a 32-bit RISC design, but was later extended to 64-bit registers and datapath. An independent administrative body called SPARC International manages the architectural specification of the SPARC V9 instruction set.

Several companies have used variants of the SPARC architecture in their products, most prominently Sun (now owned by Oracle) and Fujitsu.


Previously owned by Silicon Graphics, but now independent again, MIPS Technologies develops and licenses 64- and 32-bit architectures in the form of small, low-power "cores" that companies can incorporate into SoC (system on a chip) products. The 64-bit architecture is an extension of an earlier 32-bit RISC instruction set architecture.


Startup company Tilera is designing scalable multicore chips for embedded applications containing 32-bit or 64-bit VLIW (very long instruction word) processors suited to massively parallel applications. The web site does not describe the ISA (instruction set architecture) in any detail.

64-bit ARM?

The British chip designer ARM presently offers only a 32-bit architecture with a large share of the worldwide market for embedded processors produced by many licensees. There are not yet any 64-bit ARM processors.

Abandoned 64-bit processors

Technological trends, development costs, and sequences of consolidations among corporations in the industry have led to a decrease in the number of truly different 64-bit architectures. We list here the final offering in former product lines.

Alpha (Digital Equipment Corporation, Compaq, Hewlett-Packard)

Implementing a de novo 64-bit RISC architecture, Alpha chips were introduced in 1992 for use in scientific workstations and servers. The final EV7 (a.k.a 21364) Alpha chip was released by Hewlett-Packard in 2003 for use in server products that were then discontinued in 2006.

PA-RISC (Hewlett-Packard)

Implementing a RISC architecture first designed in 1986 for 32 bits and extended to 64 bits a decade later, PA-RISC chips were used in numerous scientific workstations and server systems. The final PA-8900 chip was released by Hewlett-Packard in 2006 for use in the final generation of RISC-based servers that were discontinued in 2008.

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