Itanium® Architecture for Programmers

Book Support

The field of computer architecture is not static, and indeed Chapter 13 of our book sketches some of the technological and market forces that drive the development of new processor implementations and/or extensions to computer architectures. On this page, we provide both updates and corrections or clarifications that have come to our attention since the book was printed.

Updated information about new Itanium 2 processors

New Itanium 2 processors have been released, formerly code-named Madison (June 2003) and Deerfield (September 2003). In order to fit these processors into the context of our book, we have prepared an electronic Appendix U: Update for New Implementations. This document contains revised versions of Tables 4-3 and 13-1 from the book, as well as pertinent new references.

Substantive errata for the book

Page i, 2nd paragraph, 2nd line:
Correct spelling is "Itanium"
Page xxxiv, add a trademark:
SSH is a registered trademark of SSH Communications Security Oy.
Page 99, Table 4-3, row with L3 information:
Total Size: up to 6MiB
Type: up to 24-way
Integer Load Latency Cycles: 12-14+
Floating Load Latency Cycles: 21-23+
Instruction Load Latency Cycles: 14+
Page 108, two lines below Figure 4-5:
change (V, V+8, V+16) to (V, V+2, V+4)
Page 252, Section 8.7.3, last paragraph, line 1:
change 16 to 32
Page 398, Table 13-1, column for Itanium:
operating voltage: 1.6 V
Page 499, fix answers:
5.b 0 if bit <7> of immediate operand is 0, otherwise complemented from register contents
5.c unchanged if bit <7> of immediate operand is 0, otherwise 1
5.d unchanged if bit <7> of immediate operand is 0, otherwise complemented from register contents
Page 513, add entries:
fib101, 371-373
FIB3 function, 332-333
Page 523, add entries under Programs:
fib101, 371-373
FIB3 function, 332-333


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